3PAR P10000 Architecture

3PAR P10000 Architecture:

A look at the 3PAR architecture and how all the components fit in.

3PAR Architecture and how the components fit in the 3PAR rack:

Note: The Controller Node shown in this picture in of T-series, for actual picture of P10000 series controller node refer to the post on HP 3PAR P10000 Components.

3PAR Architecture

Full - Mesh Back-Plane: The Controller Nodes are connected to the backplane and the communication between the nodes happens here. The Back-Plane does not have any active components and in general does not fail (unless for physical damage). The total Back-Plane bandwidth is 112GB/s.

Controller Nodes: Controller Nodes always comes in pairs. It contains 2 X 3PAR GEN4 ASIC for backend operations (RAID calculation, writing / reading data from disks) and 2 X Intel quad core processor to process the control informations. The data cache and control cache are mutually exclusive. The 3PAR GEN4 ASICs make use of the data cache and the Intel processor make use of the control cache.

Drive Chassis: The drive chassis contains 10 magazines and its numbered from 0 through 9. Each magazine contains 4 disk drives (numbered from 1 through 4) and  hence a single drive chassis can contain 40 disks. A drive chassis can a mixture of drives (SSD, FC, NL), but a magazine should hold only one type of disk. In general, the magazine 0 and 9 are said to relatively faster than those at the middle.